library verilog;
use verilog.vl_types.all;
entity PFD is
    port(
        count_clk       : in     vl_logic;
        ref_clk         : in     vl_logic;
        motor_clk       : in     vl_logic;
        count_out       : out    vl_logic_vector(15 downto 0)
    );
end PFD;
